Fig 2.1 Original PDP-8/I (Source: www.highgate.comm.sfu.ca/pdp8)
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2 |
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Processor Details |
2.1 Processor Overview
The DEC PDP-8 is a 12-bit accumulator based processor. There were many variations of the PDP-8 released. This project looks at the PDP-8/I, the most common version, which executes an instruction set common to all other releases of the PDP-8.
The processor is a CISC machine, since it has memory to memory operations and has a micro-coded instruction set with variable length execution. With only 8 basic instructions, there is considerable use made of the 17 micro-coded instructions. As standard the PDP-8 was shipped with 48KBytes of memory, addressable in 12-bit words and divided up into 32 equally sized pages of 128 words.
Fig 2.1 Original PDP-8/I (Source: www.highgate.comm.sfu.ca/pdp8)
2.2 Processor Specification
12 Bits: This means addressing is 12 bits, giving 212 locations, all instructions are 12 bits long.
A 12 bit unsigned counter, starting with an initial value of 2008
There is only one user register, which is 12 bits wide. This is known as AC. This causes many problems with only being able to store one value in the processor at any one time. In addition to the AC there is a single bit register called Link. This is used to store arithmetic overflow and values during rotation.
The 4K of memory is divided up into 32 pages each of 128 words. All pages are available for users, apart from page 0, (generally) reserved for the operating system and I/O operations. The main reason for paging is that there are not enough bits in an instruction to allow a full address to be included. This can be seen from the instruction set where only 7 bits are used to give the memory location. 7 bits will give any location within a 128 word page. The programmer is restricted to accessing either the current page or the zero page on any given instruction. If accesses are required to any other page then indirect addressing must be used, where the full 12 bit address is stored in another memory location.
Because page 0 is usually reserved, programs are written to start on page 1. At power on, the PDP-8 initialises the program counter to be 2008 (the start of page 1).
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12 bits |
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OP Code |
Indirect Bit |
Page Bit |
Page Offset |
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3 bits |
1 bit |
1 bit |
7 bits |
Fig 2.2 Instruction Format
The OP code specifies the operation that this instruction is to perform (see Fig 2.3 for a full list). The first 3 bits are always the OP code, even for micro-coded instructions.
The Indirect bit specifies whether to use direct or indirect addressing.
(0 = direct 1 = indirect). This will be explained in more detail later.
The page bit specifies whether the memory location is on the current page or the zero page (0 = zero page, 1 = current page). This means that to refer to a memory location on a page, which isn’t the current page or the zero page, indirect addressing must be used.
The final 7 bits specify the page offset. This is offset in the current or zero page, depending on the page bit.
Page Bit = 0
Real Address = "00000" concatenated with the page offset
Page Bit = 1
Real Address = Top 5 bits of the Program Counter concatenated with the page offset.
2.3 Basic Instruction Set
There are eight basic instructions in the PDP-8, these are shown in Fig 2.3.
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OP Code |
Mnemonic |
Description |
Operates on |
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0002 |
AND |
Logical 12 bit AND |
AC Ÿ MEM ® AC |
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0012 |
TAD |
Two’s Compliment ADD |
AC (+) MEM ® AC |
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0102 |
ISZ |
Increment and skip on 0 |
MEM ® MEM |
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0112 |
DCA |
Deposit and Clear AC |
AC ® MEM |
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1012 |
JMP |
Jump |
MEM ® PC |
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1002 |
JMS |
Jump Sub Routine |
PC ® MEM, MEM ® PC |
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1102 |
IOT |
I/O Transfer |
AC ® I/O, I/O® AC |
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1112 |
OP |
Micro-coded Operation |
Fig 2.3 Base instruction set table
AND instructions are as shown in fig 2.3, a logical and of the accumulator and the contents of memory as specified in the instruction. The AND instruction does not have any effect on the link bit. TAD, twos compliment addition also operates on AC and memory, but if overflow occurs the link bit is used to store the overflow.
JMP, Jump, instructions are unconditional jumps to the 7-bit address in the instruction, giving a jump range anywhere within the current page. For longer jumps can be achieved using indirect address where the 12-bit address is stored in a memory location. This makes the full range of memory available to any jump instruction.
The Skip (
ISZ) instruction provides conditional jump functionality. The skip instruction increments the memory location given in the instruction. If the result of this increment is 0008, then the next instruction is not executed. The skip instruction will take a value from memory, increment it and then write it back to memory. There is no change to the accumulator. So in the following sequence of code:TAD X
ISZ Y
TAD Z
AND V
If
Y is 7778 then ISZ will increment this to 0008 since all number are treated as two’s complement. In this case the TAD Z would not be executed, and the AND V instruction would be executed next. This kind of instruction makes looping exceptionally simple, as the loop counter needs to be –(n-1).Deposit (
DCA) instructions are store to memory operations. The instruction stores the contents of AC to memory, but then clears AC when the store is complete, under the assumption that a new value will be loaded in the AC.Jump Sub-Routine (
JMS) instruction allows sub-routine calls and a method for sub-routine returns. If a program jumps to a sub routine at location X then the program counter is stored in location X and the value X+1 is written to the program counter. This means that the first memory location of a subroutine stores the return address, the first line of code is located in the second location in the subroutine.SUBR, .-.
IAC
JMP I SUBR
*0200
JMS SUBR
The above code shows how a program would call and return from a subroutine. The subroutine (
SUBR) will increment the accumulator.A return from subroutine is achieved by jumping indirectly through the first location of the subroutine, containing the return address. This mechanism provides the ability to have nested subroutine calls, but not recursion. It is the responsibility of the programmer to store the return address before calling a subroutine recursively. This style of subroutine is not used in modern processors due to the use of a stack.
The I/O class of instruction is a complex set of instructions, which are micro-coded to allow interfacing with external devices. (Full list available in Appendix)
To provide more functionality the PDP-8 has microcoded instructions. Micro-coded instructions are where a number of instructions are encoded into one instruction. It is usual to have one bit to specify if an instruction is present in the microcode. Since there is no space to specify a memory location the data to operate on is normally explicit.
2.4 Microcoded Instructions
Microcoded Instructions are divided into two groups. The table below shows the instructions in detail:
Group 1
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1 |
1 |
1 |
0 |
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1 |
CLA |
Clear AC |
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1 |
CLL |
Clear Link |
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1 |
CMA |
Complement AC |
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1 |
CML |
Complement Link |
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1 |
0 |
0 |
RAR |
Rotate Right AC & Link |
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0 |
1 |
1 |
RAL |
Rotate Right AC & Link |
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1 |
0 |
1 |
RTR |
Rotate Right AC & Link Twice |
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0 |
1 |
1 |
RTL |
Rotate Right AC & Link Twice |
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1 |
IAC |
Increment AC & Link |
Group 2
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1 |
1 |
1 |
1 |
0 |
For future extension |
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1 |
CLA |
Clear AC |
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1 |
0 |
SMA |
Skip on AC < 0 |
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1 |
0 |
SZA |
Skip on AC = 0 |
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1 |
0 |
SNL |
Skip on Link < 0 |
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1 |
1 |
SPA |
Skip on AC > 0 |
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1 |
1 |
SNA |
Skip on AC != 0 |
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1 |
1 |
SZL |
Skip on Link = 0 |
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1 |
OSR |
OR Switches with AC |
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1 |
HLT |
Halt |
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Fig 2.4 Microcoded instruction set description (Source: DEC PDP-8 FAQ)
The fourth bit determines which group an instruction is in. All these instructions are self explanatory, with the exception of OSR. The OSR instruction is unusual in that it OR’s the contents of the accumulator with the value entered using the switches on the front panel of the original PDP-8.
A microcoded instruction may contain several instructions that need to be executed in a certain order. The following table shows the execution priority:
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Priority |
Group 1 |
Group 2 |
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1 |
CLA, CLL |
Skips |
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2 |
CMA, CML |
CLA |
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3 |
IAC |
OSR, HLT |
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4 |
Rotations |
Fig 2.5 Microcoded execution ordering
Interrupts are supported by the PDP-8 in a very simple way. If an interrupt occurs, then on completion of the current instruction the processor will force a sub-routine into the instruction register, whose target is location 0008. It is then up to the programmer to handle the interrupts with code beginning at location 0018 since the return address is stored in location 0008. There are also two additional instructions encoded into the I/O instruction. ION and IOF enable and disable interrupt response, respectively. It is usual practice to turn interrupts off during an interrupt handler, then enable them before returning to the interrupted code.
The PDP-8 supports auto indexing in memory locations 0108 to 0178. Auto indexing is a method to improve speed by incrementing a value in memory on each access to that value. It is especially useful when indexing arrays of data inside a loop.